1. Field of the Invention
The present invention relates to a method for fabricating a parallel gate matrix circuit in a self-alignment type metal oxide semiconductor large scale integration circuit (hereinafter referred to as MOS LSI).
2. Description of the Prior Art
In the MOS LSI, in order to reduce a parastic capacitance in the circuit to improve a frequency characteristic thereof, a method for manufacturing transistors by a so-called self-alignment technique has been frequently used.
FIG. 1 of the accompanying drawings is a sectional view of an MOS field-effect transistor fabricated in a silicon substrate by a conventional self-alignment technique, and the MOS field-effect transistor comprises a gate section consisting of a gate oxide layer 2 formed on a silicon substrate 1 having a type of conductivity and a gate electrode layer 3 formed on the gate oxide layer 2, and a drain region 4 and a source region 5 each having a type of conductivity opposite to that of the silicon substrate.
In the figure, numeral 6 designates a silicon dioxide layer formed during the diffusion processing of the drain and source regions, which constitutes a field oxide layer as usually known. With the self-alignment technique, it has been customary to use a material, e.g., polycrystalline silicon or molybdenum for the gate electrode layers so that the gate section consisting of this gate electrode layer and the gate oxide layer formed thereunder serves as a mask during the diffusion of the drain and source regions.
In an MOS field-effect transistor fabricated in this manner, there is practically no drain and source regions formed in overlapping relation directly under the gate section and thus this type of MOS field-effect transistor has a reduced effective capacitance per unit area of gate and an improved frequency characteristic.
FIGS. 2a and 2b illustrate an enlarged portion of a large scale integration circuit fabricated by utilizing the self-alignment technique described above, with FIG. 2a showing a plan view of the enlarged portion and FIG. 2b showing a sectional view taken along the line A -- A of FIG. 2a.
In FIG. 2a, numerals 7, 8, 9 and 10 designate gate electrode layers consisting of molybdenum, for example, and diffused regions (hatched portions) having a type of conductivity opposite to that of the silicon substrate are formed on both sides of the respective gate electrode layers. In the construction shown in FIG. 2a, the diffused regions are indicated by numerals 11 through 15. Thus, MOS field-effect transistor is provided by each gate electrode layer portion having the diffused regions formed on both sides thereof as shown at 16 in the figure.
FIG. 2b is a sectional view taken along the line A -- A of FIG. 2a to more clearly show the structure of the fabricated MOS field-effect transistor and, as will be seen from this figure, each of the diffused regions provides a drain region and a source region for different ones of the MOS field effect transistors. Numerals 17 through 20 designate the gate oxide layers.
The application of this self-alignment technique results in the fabrication in a silicon substrate of a plurality of MOS field-effect transistor groups each thereof having their gate electrodes connected in common.
Consequently, if it is desired to produce a matrix circuit by utilizing the MOS field-effect transistors fabricated in a silicon substrate in this way, the resultant matrix circuit must take the form of a series gate circuit.
In short, a drawback of the prior art self-alignment fabrication method is that it is impossible to manufacture parallel gate type matrix circuits.